A pervasive trend in modern integrated circuit manufacture is to increase the amount of data stored per unit area on an integrated circuit memory unit, such as a flash memory unit. That is, as flash memory technology progresses, the speed and memory density becomes higher and higher. Modern flash memory units are characterized by the non-volatility of the charge stored in the arrays of memory cells that make up the memory unit.
Due to the high density of charge storing cells, various techniques for improving process margin in memory unit fabrication have been employed. One technique is to place dummy wordlines adjacent a top wordline and a bottom wordline of a memory cell array.
From time-to-time, use of the memory unit may involve erasing some or all of the cells. For example, to erase an array of floating gate memory devices or an array of dielectric charge trapping memory devices, a relative large negative gate voltage (e.g., about −9.3 volts in the case of floating gate memory devices) can be applied to the wordlines of the array for a predetermined amount of time (or “pulse” duration). Bitlines of the array can be grounded during the erase operation. Also during the erase operation, a first dummy wordline adjacent the top wordline and a second dummy wordline adjacent the bottom wordline can be grounded.
This arrangement can lead to coupling between top wordline and the first dummy wordline and between the bottom wordline and the second dummy wordline during the erase operation. In the cells defined by the top wordline and the bottom wordline (referred to respectively as the top row of cells and the bottom row of cells), the threshold voltage (Vt) distribution can become degraded due to the coupling and erasing these cells can take a relatively long time. For example, with reference to FIG. 1, shown is a graph of the threshold voltage (Vt) distribution for the cells of a conventionally erased floating memory cell array. A first distribution curve C1 corresponds to the threshold voltage distribution for the wordlines disposed between the top and bottom wordlines (or middle wordlines) where insubstantial coupling to adjacent dummy wordlines is present. A second distribution curve C2 corresponds to the threshold voltage distribution for the top wordline and the bottom wordline where coupling to the dummy wordlines during the erase operation occurs. As shown graphically, the curve C2 is upwardly shifted relative to the curve C1. A difference between the curves, or delta Vt, can be about 1 volt. As indicated, this difference can slow erase operation of the top and bottom row of the array. As a result, the middle rows of cells will have a tendency to erase faster than the top and bottom rows of cell.
If erase speed is slowed too much, the top and bottom rows of cells may not become fully erased during application of the erase pulse. For example, a portion of the distribution curve C2 may be above a desired erase threshold voltage (Vt—erase). If the top and bottom rows of cells do not pass an erase verification, it is possible to re-erase the sector of memory cells. Alternatively, a longer erase pulse could be used. But the coupling described above and any corrective operation tend to push the memory cells into depletion mode, which leads to wider erase distributions and poor flash memory device operation.
Accordingly, there exists a need in the art to improve erasing of a memory array that includes dummy wordlines.